Which of the following digital logic families has the lowest power consumption?

Explanation

In a settled CMOS gate the P-channel and N-channel transistors are never both conducting, so quiescent current is little more than leakage and power is spent mainly during transitions, rising with capacitance, the square of supply voltage, and clock rate. Schottky TTL, ECL, and NMOS all draw steady current through their output stages whatever the logic state.